Z80 user manual

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Carry Flag. Decimal Adjust Accumulator Flag. Half Carry Flag. Zero Flag. Sign Flag. Z80 Instruction Description. LD r, r'. LD r,n. LD r, HL. LD A, BC. LD A, DE. LD A, nn. LD A, I. LD A, R. LD I,A. LD R, A. LD dd, nn. LD IX, nn. LD IY, nn. LD HL, nn. LD nn , HL. LD nn , dd. LD nn , IX. LD nn , IY. PUSH qq. POP qq. POP IX. POP IY. ADD A, r. ADD A, n. ADC A, s.

SUB s. SBC A, s. AND s. XOR s. INC r. INC HL. DEC m. ADD HL, ss. ADC HL, ss. SBC HL, ss. ADD IX, pp. ADD IY, rr. INC ss. INC IX. INC IY. DEC ss.

DEC IX. DEC IY. RLC r. RLC HL. RRC m. SLA m. SRA m. SRL m. BIT b, r. BIT b, HL. SET b, r. SET b, HL. RES b, m. JP nn. JP cc, nn.

JR C, e. JR NC, e. JR Z, e. JR NZ, e. JP HL. JP IX. JP IY. DJNZ, e. CALL nn. CALL cc, nn. RET cc. RST p. IN A, n. Customer Support. UM List of Figures. Figure 1. Figure 2. CPU Register Configuration. Figure 3.

Figure 4. Figure 5. Instruction Op Code Fetch. Figure 6. Memory Read or Write Cycle. Figure 7. Figure 8. Figure 9. Figure Fill effortlessly with an upgraded revolving cap.

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M1 together with IORQ, indicates an interrupt acknowledge cycle. Memory Request output, active Low, tristate. MREQ indicates that the address bus holds a valid address for a memory read of memory write operation. Non-Maskable Interrupt input, negative edge-triggered. NMI is always recognized at the end of the current instruction, independent of the status of the interrupt enable flipflop, and automatically forces the CPU to restart at location H.

Read output, active Low, tristate. Reset input, active Low. During reset time, the address and data bus go to a high-impedance state, and all control output signals go to the inactive state. Notice that RESET must be active for a minimum of three full clock cycles before the reset operation is complete. Refresh output, active Low. WAIT input, active Low.

Write output, active Low, tristate. This signal is sampled at the same time as the interrupt line, but this line takes priority over the normal interrupt and it can not be disabled under software control.

Its usual function is to provide immediate response to important signals such as an impending power failure. The CPU response to a non-maskable interrupt is similar to a normal memory read operation. The only difference is that the content of the data bus is ignored while the processor automatically stores the PC in the external stack and jumps to location H.

The service routine for the nonmaskable interrupt must begin at this location if this interrupt is used. ELW Welcome to ManualMachine. We have sent a verification link to to complete your registration. Log In Sign Up. Forgot password? Enter your email address and check your inbox. Please check your email for further instructions. Enter a new password. The external circuitry can now control these lines. Clock input. Single-phase MOS-level clock.

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